RTL Design Engineer

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MTS SILICON DESIGN ENGINEER
THE ROLE:
AMD-Xilinx is seeking a capable and motivated SOC Design Engineer to be part of Front End SOC Design Team of next generation Adaptable Compute Acceleration Platform devices
You will take part in design and implementation of high-performance, low-power SOCs and SOC Chiplets targeting a wide range of applications as well as customer specific products
This high visibility and critical role will require technical leadership in developing microarchitecture, implementing functions in RTL, integrating IP from internal and external sources, ensuring quality and getting design ready for synthesis.
You will also contribute to definition/evolution of SOC Design methodologies and processes for future projects
THE PERSON:
Successful candidate will have an SOC/ASIC Design background, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution
KEY RESPONISIBILITES:
Analyze existing design blocks for faults and vulnerabilities as application to automotive usage
Define and specify micro-architecture of future SOC building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
RTL design and debug of functions in Verilog / System Verilog
Integration of hard macro or soft RTL IP into SOC top level
Power domain/island creation (with UPF)
Execution of quality checks to improve quality of RTL/UPF/SDC deliverables
Analysis of design metrics and making implementation choices to optimize PPA
Targeting SOC RTL to process technology
Facilitating DFx/MBIST instrumentation
Work with verification and physical design teams to achieve high quality design and successful tape out
Collaborate with cross-functional teams to solve novel problems across multiple functional areas
Design and implement underlying Power Management, Clk/Rst, NOC and DFT infrastructures to ensure implementation tool requirements are met and are optimized for compile time and memory
Participate in tapeout checklists and reviews
Build automation (Python, TCL, Perl) to enhance productivity of self and team
PREFERRED EXPERIECE:
Digital design and experience with RTL design in Verilog/System Verilog
Solid understanding of DFT technologies and some experience with execution of DFT flows
Experience with SOC tools including Spyglass, Questa CDC, Cadence Conformal, VCS simulation
Experience in specifying timing constraints with several clock domains and modes
Basic experience with Synopsys Design Compiler and Primetime
Experience designing with multiple power domains and islands using UPF
Floor-planning and partitioning
TCL, Python, Perl scripting
Version control systems such as Perforce, IC Manage or Git
Understanding of FPGA architecture and implementation flow
Strong verbal and written communication skills
Ability to organize and present complex technical information
Fluent in working with Linux environment
Academic Credentials and Experience
Will use HR Guidelines for grade. This information is not published in job posting.
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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.