AI Full-Chip Floorplanning - Physical Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are seeking an adaptive, self‑motivated Physical Design Engineer to join our growing team. As a key contributor, you will help drive AMD’s capabilities in delivering high‑performance, power‑efficient silicon solutions. The Physical Design team values continuous technical innovation and supports professional growth through challenging projects and collaborative success.
In this role, you will be responsible for full‑chip floorplanning, physical implementation, timing closure, and power optimization across complex SoC designs, while also leveraging AI‑assisted physical design methodologies—including ML‑based macro placement (MLMP) and design space optimization (DSO / DSO.ai)—to accelerate convergence and improve quality of results.
THE PERSON:
You are passionate about modern, complex processor architectures and bring deep expertise in physical implementation flows. You have strong experience in full‑chip floorplanning, synthesis, place and route, timing closure, and power optimization, along with a curiosity for applying AI‑driven and data‑guided optimization techniques to physical design challenges.
You are a collaborative team player with strong communication skills and a history of working across geographies and disciplines. You possess excellent analytical and problem‑solving abilities, are eager to learn new methodologies (including AI‑enabled flows), and thrive in tackling complex SoC‑level design challenges.
KEY RESPONSIBILITIES:
Define chip‑level partitioning, block placement strategy, and macro integration to meet design, performance, and power goals
Demonstrate hands‑on expertise in full‑chip floorplanning, including feedthrough topology planning, repeater (repeat) insertion, top‑level port/pin assignment and alignment, and source‑synchronous bus layout
Optimize full‑chip floorplans for timing, power, area, and routability, incorporating feedback from downstream physical implementation and signoff stages
Apply AI‑assisted floorplanning and optimization techniques, including ML‑based Macro Placement (MLMP) and DSO / DSO.ai‑driven design space exploration, to reduce manual iterations and improve QoR
Collaborate closely with RTL, physical design, timing, power, and architecture teams to gather requirements and drive floorplan convergence
Conduct layout feasibility studies through what‑if analysis, trade‑off evaluations, and design space exploration
Utilize industry‑standard EDA tools such as Cadence Innovus, Synopsys ICC/Fusion Compiler, DSO.ai, and Calibre for physical implementation and verification
Develop and maintain automation scripts using Tcl, Perl, and Python to improve floorplanning productivity, repeatability, and consistency
Apply low‑power design techniques; familiarity with voltage domain crossing checks and multi‑voltage floorplanning is a strong asset
PREFERRED EXPERIENCE:
Extensive experience in SoC physical implementation and tapeout, including full‑chip responsibilities
Strong expertise in physical design methodologies, flows, and best practices
Proficiency with Synopsys Fusion Compiler (FC) and exposure to DSO / DSO.ai or similar optimization frameworks
Experience with AI‑assisted physical design techniques, such as ML‑based macro placement or design space optimization, is highly desirable
Solid understanding of SoC architecture and design, including AXI buses, source‑synchronous interfaces, and test design considerations
Demonstrated experience with full‑chip timing‑aware floorplanning, timing quality checks, and integration with timing closure teams
Highly committed to meeting project milestones with high‑quality deliverables
Proven ability to collaborate effectively with IP, timing, power, and PD teams to achieve closure
Excellent communication skills; capable of working independently and within globally distributed teams
Demonstrated leadership, ownership, and strong teamwork capabilities
Skilled in Perl, Shell, Tcl scripting, and familiarity with Verilog RTL is a plus
ACADEMIC CREDENTIALS:
Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or a related field.
LOCATION: Markham, ON
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.