Staff Silicon Design Engineer (FEINT)

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
We are looking for an adaptive, self-motivative physical design engineer to join our team. As a key contributor, you will be part of a engineering team to drive and improve AMD's abilities to deliver the MI/Navi series of GPU products to market. The Frontend integration(FEINT) Engineering team, as part of GE SoC team, furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE PERSON:
You have a passion for cutting-edge semiconductor technology, digital design, and physical design in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
Design synthesis: Performing logical and physical synthesis of blocks
Design analysis: Analyzing and verifying that the design meets requirements for functionality, performance, and area
Design constraints: Defining synthesis design constraints and resolving STA issues
Timing analysis: Analyzing timing arc and liberty quality, and providing suggestions for fixing timing violations
Design quality checks: Completing all design quality checks and data quality checks (CDC/RDC/LINT/No clock flops etc)
Collaboration: Working with RTL engineers to fix timing issues
Tool evaluation: Driving new tool evaluation and methodology refinement
ECO Implementation :Develop/enhance auto ECO generation scripts for timing closure and ECO implementation
Power: Low power optimizations/UPF
scripting for daily task automation and data analysis
PREFERRED EXPERIENCE:
Familiar with EDA tools (Fusion compiler, Prime Time, Formality, Conformal Lec, Conformal ECO, cdc0in, VC spyglass etc)
Good at TCL/shell/perl/python programming
Familiar with Unix/Linux environment
Familiar with Verilog, System Verilog
Strong analytical and problem solving skills with pronounced attention to detail
Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality
ACADEMIC CREDENTIALS:
Bachelors or Masters degree in Electronic engineering/Electrical Engineering.
LOCATION:
Penang, Malaysia
#LI-KL1
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.