SDC Timing constraints Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
MTS SILICON DESIGN ENGINEER
About the Role
We are seeking a highly skilled and motivated Member of Technical Staff (MTS) to join our Speedfiles team. In this role, you will drive timing capture across complex, high‑performance SoC/IP blocks, working closely with physical design, RTL, methodology, and architecture teams. The ideal candidate has strong hands-on STA expertise, a deep understanding of semiconductor timing fundamentals, and a passion for delivering high-quality silicon.
Key Responsibilities
Own and execute block-level static timing capture, including constraint development
Validate timing constraints (SDC) for different modes
Perform timing capture across multiple corners and modes to identify, debug, and resolve timing related issues
Collaborate with RTL, PD, and synthesis teams to influence for optimal timing.
Work closely with the methodology team to improve Timing capture flows, automation, reports, and signoff processes.
Debug and resolve complex issues involving noise, crosstalk, OCV, POCV, AOCV, and IR-drop impacts.
Support silicon bring-up by correlating pre‑silicon STA results with post‑silicon timing behavior.
Document and present timing capture status, risks, and strategies to cross‑functional teams and management.
Required Qualifications
Bachelor’s or Master’s degree in Electronics Engineering, VLSI, or related fields.
7–10 years of hands-on experience in STA for high-performance SoCs or IPs.
Strong expertise with industry-standard STA tools:
Synopsys PrimeTime/Cadence Tempus
Solid understanding of:
Timing fundamentals (setup, hold, transition, constraints)
Multiple corners and modes analysis
Clocking architecture and CTS concepts
Cross-talk, OCV/AOCV/POCV, and derating techniques
Proven experience with timing ECOs and convergence strategies.
Proficiency with scripting languages:
TCL, Perl, Python, or Shell scripting.
Excellent analytical, debugging, and problem-solving skills.
Strong communication skills and ability to collaborate in a multi-site environment.
Preferred Qualifications
Experience in advanced technology nodes (7nm, 5nm, 3nm or similar).
Exposure to signoff flows, methodology development, and automation.
Knowledge of physical design stages (floorplanning, placement, CTS, routing) to guide PD teams effectively.
Familiarity with DFT constraints, scan STA, and low-power timing (e.g., level shifters, retention cells).
Background in high-speed interfaces, CPU/GPU IPs, or large SoC designs.
#LI-RP1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.